The conventional manner of storing a matrix in a digital computer's memory is by storing the matrix elements in rows with individual matrix elements of each row stored in consecutive memory locations. A problem arises when a decrease in the effective access time of a memory is attempted by interleaving M memory modules (each having N words) into one memory with all locations whose addresses are of the form KM being in one module, the locations of the form KM+1 being in another module and so on. When each of the elements of a row in a matrix are stored in consecutive, interleaved modules of an interleaved memory, the accessing of a matrix row can proceed at a very rapid rate, i.e., M elements of the row are returned in one memory module access time. However, the "corner turning" problem occurs when it is a column that is desired to be accessed rather than a row. Since all of the matrix elements of a column are in the same memory module, the interleaved operation of the overall memory will not speed up the access rate for the matrix column (only one column element returned in one memory module access time).
In most pipelined signal or vector matrix processors, the data must originate at some point in a single main memory and the answers must return there. Since memory technology speeds are increasing at a slower rate than processor logic technology, there is an increasing gap between processor and memory speeds. The primary technique to speed up memories is interleaving. But this interleaving technique fails to solve the problem of accessing either row or column components of a matrix at the same fast rate. The memory is the bottleneck in the state of the art matrix processor.